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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-04-23 22:00:09 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-05-02 16:49:34 +0200 |
| commit | df44e81703968d22ce59e1160f970c5e70db2cfb (patch) | |
| tree | 573129393cdea3ea7d4255c11964c28a4947c75a /target/mips/translate.h | |
| parent | bc2eb5ea1b595fb686b7bef81bbf20e6a9635476 (diff) | |
target/mips: Migrate missing CPU fields
Add various missing fields to the CPU migration vmstate:
- CP0_VPControl & CP0_GlobalNumber (01bc435b44b 2016-02-03)
- CMGCRBase (c870e3f52ca 2016-03-15)
- CP0_ErrCtl (0d74a222c27 2016-03-25)
- MXU GPR[] & CR (eb5559f67dc 2018-10-18)
- R5900 128-bit upper half (a168a796e1c 2019-01-17)
This is a migration break.
Fixes: 01bc435b44b ("target-mips: implement R6 multi-threading")
Fixes: c870e3f52ca ("target-mips: add CMGCRBase register")
Fixes: 0d74a222c27 ("target-mips: make ITC Configuration Tags accessible to the CPU")
Fixes: eb5559f67dc ("target/mips: Introduce MXU registers")
Fixes: a168a796e1c ("target/mips: Introduce 32 R5900 multimedia registers")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210423220044.3004195-1-f4bug@amsat.org>
Diffstat (limited to 'target/mips/translate.h')
0 files changed, 0 insertions, 0 deletions