diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2023-05-02 14:57:37 +0100 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-05-05 17:05:28 +0100 |
| commit | 6d0cad12594243375b255de76cc10f9b607cb2c9 (patch) | |
| tree | 0d78c6685eac0cd1841cf460c0e5b6c8366ae268 /target/mips/tcg | |
| parent | b7a94da9550be04441ffd91f0865d604c8a804cd (diff) | |
target/mips: Finish conversion to tcg_gen_qemu_{ld,st}_*
Convert away from the old interface with the implicit
MemOp argument.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230502135741.1158035-6-richard.henderson@linaro.org>
Diffstat (limited to 'target/mips/tcg')
| -rw-r--r-- | target/mips/tcg/nanomips_translate.c.inc | 2 | ||||
| -rw-r--r-- | target/mips/tcg/translate.c | 8 |
2 files changed, 5 insertions, 5 deletions
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc index 9398e28000..97b9572caa 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -998,7 +998,7 @@ static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset, TCGv tmp2 = tcg_temp_new(); gen_base_offset_addr(ctx, taddr, base, offset); - tcg_gen_qemu_ld64(tval, taddr, ctx->mem_idx); + tcg_gen_qemu_ld_i64(tval, taddr, ctx->mem_idx, MO_TEUQ); if (cpu_is_bigendian(ctx)) { tcg_gen_extr_i64_tl(tmp2, tmp1, tval); } else { diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 999fbb7cc1..a6ca2e5a3b 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1949,13 +1949,13 @@ FOP_CONDNS(s, FMT_S, 32, gen_store_fpr32(ctx, fp0, fd)) /* load/store instructions. */ #ifdef CONFIG_USER_ONLY -#define OP_LD_ATOMIC(insn, fname) \ +#define OP_LD_ATOMIC(insn, memop) \ static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \ DisasContext *ctx) \ { \ TCGv t0 = tcg_temp_new(); \ tcg_gen_mov_tl(t0, arg1); \ - tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \ + tcg_gen_qemu_ld_tl(ret, arg1, ctx->mem_idx, memop); \ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, lladdr)); \ tcg_gen_st_tl(ret, cpu_env, offsetof(CPUMIPSState, llval)); \ } @@ -1967,9 +1967,9 @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \ gen_helper_##insn(ret, cpu_env, arg1, tcg_constant_i32(mem_idx)); \ } #endif -OP_LD_ATOMIC(ll, ld32s); +OP_LD_ATOMIC(ll, MO_TESL); #if defined(TARGET_MIPS64) -OP_LD_ATOMIC(lld, ld64); +OP_LD_ATOMIC(lld, MO_TEUQ); #endif #undef OP_LD_ATOMIC |