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| author | Peter Maydell <peter.maydell@linaro.org> | 2022-07-13 21:48:16 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-07-13 21:48:16 +0100 |
| commit | 455c62d85f72037ea3ca4b709ad73965c65158b2 (patch) | |
| tree | 4b9aedcbd166b673ab00f49d63edb50803712673 /target/mips/tcg/octeon.decode | |
| parent | 824824d12217f7d80b372eb051aad2c082cffb98 (diff) | |
| parent | b10ccec10096a27bb3b99a7291d5a3d5c826a1f3 (diff) | |
Merge tag 'mips-20220712' of https://github.com/philmd/qemu into staging
MIPS patches queue
- Cavium Octeon MIPS extension and CPU model (Pavel Dovgalyuk)
- Semihosting cleanup (Richard Henderson)
# gpg: Signature made Tue 12 Jul 2022 21:52:52 BST
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'mips-20220712' of https://github.com/philmd/qemu:
target/mips: Remove GET_TARGET_STRING and FREE_TARGET_STRING
target/mips: Simplify UHI_argnlen and UHI_argn
semihosting: Remove qemu_semihosting_log_out
target/mips: Use error_report for UHI_assert
target/mips: Avoid qemu_semihosting_log_out for UHI_plog
target/mips: Use semihosting/syscalls.h
target/mips: Drop link syscall from semihosting
target/mips: Create report_fault for semihosting
target/mips: introduce Cavium Octeon CPU model
target/mips: implement Octeon-specific arithmetic instructions
target/mips: implement Octeon-specific BBIT instructions
target/mips: introduce decodetree structure for Cavium Octeon extension
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/mips/tcg/octeon.decode')
| -rw-r--r-- | target/mips/tcg/octeon.decode | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode new file mode 100644 index 0000000000..8929ad088e --- /dev/null +++ b/target/mips/tcg/octeon.decode @@ -0,0 +1,41 @@ +# Octeon Architecture Module instruction set +# +# Copyright (C) 2022 Pavel Dovgalyuk +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# + +# Branch on bit set or clear +# BBIT0 110010 ..... ..... ................ +# BBIT032 110110 ..... ..... ................ +# BBIT1 111010 ..... ..... ................ +# BBIT132 111110 ..... ..... ................ + +%bbit_p 28:1 16:5 +BBIT 11 set:1 . 10 rs:5 ..... offset:16 p=%bbit_p + +# Arithmetic +# BADDU rd, rs, rt +# DMUL rd, rs, rt +# EXTS rt, rs, p, lenm1 +# EXTS32 rt, rs, p, lenm1 +# CINS rt, rs, p, lenm1 +# CINS32 rt, rs, p, lenm1 +# DPOP rd, rs +# POP rd, rs +# SEQ rd, rs, rt +# SEQI rt, rs, immediate +# SNE rd, rs, rt +# SNEI rt, rs, immediate + +@r3 ...... rs:5 rt:5 rd:5 ..... ...... +%bitfield_p 0:1 6:5 +@bitfield ...... rs:5 rt:5 lenm1:5 ..... ..... . p=%bitfield_p + +BADDU 011100 ..... ..... ..... 00000 101000 @r3 +DMUL 011100 ..... ..... ..... 00000 000011 @r3 +EXTS 011100 ..... ..... ..... ..... 11101 . @bitfield +CINS 011100 ..... ..... ..... ..... 11001 . @bitfield +POP 011100 rs:5 00000 rd:5 00000 10110 dw:1 +SEQNE 011100 rs:5 rt:5 rd:5 00000 10101 ne:1 +SEQNEI 011100 rs:5 rt:5 imm:s10 10111 ne:1 |