diff options
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-10-19 14:22:32 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-11-02 14:32:32 +0100 |
| commit | c79db8c239fb4272de3cd0741c0ecfd549d5588a (patch) | |
| tree | 7a3ed0a556c3a56a696abd5705251f231a54fb70 /target/mips/tcg/msa.decode | |
| parent | f18708a53adc0549526fbeba5d1e892c0c4bf49c (diff) | |
target/mips: Convert MSA 3R instruction format to decodetree (part 3/4)
Convert BINSL (Vector Bit Insert Left) and BINSR (Vector Bit
Insert Right) opcodes to decodetree.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-23-f4bug@amsat.org>
Diffstat (limited to 'target/mips/tcg/msa.decode')
| -rw-r--r-- | target/mips/tcg/msa.decode | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 0e2f474cde..f2bacbaea8 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -89,6 +89,9 @@ BNZ 010001 111 .. ..... ................ @bz SRARI 011110 010 ....... ..... ..... 001010 @bit SRLRI 011110 011 ....... ..... ..... 001010 @bit + BINSL 011110 110.. ..... ..... ..... 001101 @3r + BINSR 011110 111.. ..... ..... ..... 001101 @3r + DOTP_S 011110 000.. ..... ..... ..... 010011 @3r DOTP_U 011110 001.. ..... ..... ..... 010011 @3r DPADD_S 011110 010.. ..... ..... ..... 010011 @3r |