diff options
| author | James Hogan <james.hogan@imgtec.com> | 2017-07-18 12:55:55 +0100 |
|---|---|---|
| committer | Yongbok Kim <yongbok.kim@imgtec.com> | 2017-07-20 22:42:26 +0100 |
| commit | 42c86612d507c2a8789f2b8d920a244693c4ef7b (patch) | |
| tree | 4fb67a58c82b9fb3a31b47ff97545dce9d4da58c /target/mips/op_helper.c | |
| parent | b0fc6003224543d2bdb172eca752656a6223e4a1 (diff) | |
target/mips: Add an MMU mode for ERL
The segmentation control feature allows a legacy memory segment to
become unmapped uncached at error level (according to CP0_Status.ERL),
and in fact the user segment is already treated in this way by QEMU.
Add a new MMU mode for this state so that QEMU's mappings don't persist
between ERL=0 and ERL=1.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
[yongbok.kim@imgtec.com:
cosmetic changes]
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Diffstat (limited to 'target/mips/op_helper.c')
| -rw-r--r-- | target/mips/op_helper.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index da1817e94a..c52a407e86 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -67,6 +67,7 @@ static inline type do_##name(CPUMIPSState *env, target_ulong addr, \ case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr); \ default: \ case 2: return (type) cpu_##insn##_user_ra(env, addr, retaddr); \ + case 3: return (type) cpu_##insn##_error_ra(env, addr, retaddr); \ } \ } #endif @@ -94,6 +95,9 @@ static inline void do_##name(CPUMIPSState *env, target_ulong addr, \ case 1: cpu_##insn##_super_ra(env, addr, val, retaddr); break; \ default: \ case 2: cpu_##insn##_user_ra(env, addr, val, retaddr); break; \ + case 3: \ + cpu_##insn##_error_ra(env, addr, val, retaddr); \ + break; \ } \ } #endif @@ -1451,6 +1455,9 @@ void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1) val, val & env->CP0_Cause & CP0Ca_IP_mask, env->CP0_Cause); switch (cpu_mmu_index(env, false)) { + case 3: + qemu_log(", ERL\n"); + break; case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; case MIPS_HFLAG_KM: qemu_log("\n"); break; @@ -2245,6 +2252,9 @@ static void debug_post_eret(CPUMIPSState *env) if (env->hflags & MIPS_HFLAG_DM) qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); switch (cpu_mmu_index(env, false)) { + case 3: + qemu_log(", ERL\n"); + break; case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; case MIPS_HFLAG_KM: qemu_log("\n"); break; |