diff options
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-12-16 23:59:07 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-01-14 17:13:53 +0100 |
| commit | 8b0ea9b638adadcf056f4a18fe53a7c6339beba8 (patch) | |
| tree | 25b77517bdd13f095f26af114b92b725f85c6b44 /target/mips/mips-defs.h | |
| parent | bf5523773eac7a17cf6f6a062b3311a09063881f (diff) | |
target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1
'CPU_MIPS32' and 'CPU_MIPS64' definitions concern CPUs implementing
the "Release 1" ISA. Rename it with the 'R1' suffix, as the other
CPU definitions do.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210104221154.3127610-4-f4bug@amsat.org>
Diffstat (limited to 'target/mips/mips-defs.h')
| -rw-r--r-- | target/mips/mips-defs.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 48544ba73b..1630ae20d5 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -72,12 +72,12 @@ #define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI) /* MIPS Technologies "Release 1" */ -#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32) -#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) +#define CPU_MIPS32R1 (CPU_MIPS2 | ISA_MIPS32) +#define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1 | ISA_MIPS64) /* MIPS Technologies "Release 2" */ -#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) -#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) +#define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS32R2) +#define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2 | ISA_MIPS64R2) /* MIPS Technologies "Release 3" */ #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) |