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authorPavel Dovgalyuk <pavel.dovgalyuk@ispras.ru>2022-06-20 15:05:21 +0300
committerPhilippe Mathieu-Daudé <f4bug@amsat.org>2022-07-12 22:30:09 +0200
commit72d680e4083a75c55d89c55f799cbe870ebbc7a5 (patch)
tree6e574cbcda3a178b8b3d732dfe7d2a0d34228fae /target/mips/mips-defs.h
parent8e3d85d36b77f11ad7bded3a2d48c1f0cc334f82 (diff)
target/mips: introduce decodetree structure for Cavium Octeon extension
This patch adds decodetree for Cavium Octeon extension and an instruction set extension flag for using it in CPU models. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <165572672162.167724.13656301229517693806.stgit@pasha-ThinkPad-X280> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'target/mips/mips-defs.h')
-rw-r--r--target/mips/mips-defs.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 0a12d982a7..a6cebe0265 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -42,6 +42,7 @@
#define INSN_LOONGSON2E 0x0000040000000000ULL
#define INSN_LOONGSON2F 0x0000080000000000ULL
#define INSN_LOONGSON3A 0x0000100000000000ULL
+#define INSN_OCTEON 0x0000200000000000ULL
/*
* bits 52-63: vendor-specific ASEs
*/