diff options
author | Peter Maydell <peter.maydell@linaro.org> | 2021-03-14 19:16:11 +0000 |
---|---|---|
committer | Peter Maydell <peter.maydell@linaro.org> | 2021-03-14 19:16:11 +0000 |
commit | 36d840f35b4fc7e2d47fb54313950f82690b2286 (patch) | |
tree | d27cd7a4204b050792ad6c3b223d093cb751f63d /target/mips/meson.build | |
parent | 6157b0e19721aadb4c7fdcfe57b2924af6144b14 (diff) | |
parent | d27fadddc673dd85a34102342b43be23d27eaab6 (diff) |
Merge remote-tracking branch 'remotes/philmd/tags/mips-20210313' into staging
MIPS patches queue
- Tidy up the GT64120 north bridge
- Move XBurst Media eXtension Unit code to mxu_translate.c
- Convert TX79 to decodetree
# gpg: Signature made Sat 13 Mar 2021 22:44:44 GMT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* remotes/philmd/tags/mips-20210313: (27 commits)
target/mips/tx79: Salvage instructions description comment
target/mips: Remove 'C790 Multimedia Instructions' dead code
target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetree
target/mips/tx79: Move PCPYH opcode to decodetree
target/mips/translate: Simplify PCPYH using deposit_i64()
target/mips/translate: Make gen_rdhwr() public
target/mips/tx79: Move MTHI1 / MTLO1 opcodes to decodetree
target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree
target/mips: Use gen_load_gpr[_hi]() when possible
target/mips: Extract MXU code to new mxu_translate.c file
target/mips: Introduce mxu_translate_init() helper
target/mips: Simplify decode_opc_mxu() ifdef'ry
target/mips: Convert decode_ase_mxu() to decodetree prototype
target/mips: Rename decode_opc_mxu() as decode_ase_mxu()
target/mips: Move MUL opcode check from decode_mxu() to decode_legacy()
target/mips: Use OPC_MUL instead of OPC__MXU_MUL
target/mips: Pass instruction opcode to decode_opc_mxu()
target/mips: Remove unused CPUMIPSState* from MXU functions
target/mips: Remove XBurst Media eXtension Unit dead code
target/mips: Rewrite complex ifdef'ry
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/mips/meson.build')
-rw-r--r-- | target/mips/meson.build | 18 |
1 files changed, 15 insertions, 3 deletions
diff --git a/target/mips/meson.build b/target/mips/meson.build index 9741545440..3b131c4a7f 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -3,15 +3,17 @@ gen = [ decodetree.process('mips64r6.decode', extra_args: '--static-decode=decode_mips64r6'), decodetree.process('msa32.decode', extra_args: '--static-decode=decode_msa32'), decodetree.process('msa64.decode', extra_args: '--static-decode=decode_msa64'), + decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'), ] mips_ss = ss.source_set() -mips_ss.add(gen) mips_ss.add(files( 'cpu.c', 'gdbstub.c', )) -mips_ss.add(when: 'CONFIG_TCG', if_true: files( +mips_tcg_ss = ss.source_set() +mips_tcg_ss.add(gen) +mips_tcg_ss.add(files( 'dsp_helper.c', 'fpu_helper.c', 'lmmi_helper.c', @@ -22,7 +24,15 @@ mips_ss.add(when: 'CONFIG_TCG', if_true: files( 'tlb_helper.c', 'translate.c', 'translate_addr_const.c', + 'txx9_translate.c', )) +mips_ss.add(when: ['CONFIG_TCG', 'TARGET_MIPS64'], if_true: files( + 'tx79_translate.c', +)) +mips_tcg_ss.add(when: 'TARGET_MIPS64', if_false: files( + 'mxu_translate.c', +)) + mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) mips_softmmu_ss = ss.source_set() @@ -30,11 +40,13 @@ mips_softmmu_ss.add(files( 'addr.c', 'cp0_timer.c', 'machine.c', - 'mips-semi.c', )) mips_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files( 'cp0_helper.c', + 'mips-semi.c', )) +mips_ss.add_all(when: 'CONFIG_TCG', if_true: [mips_tcg_ss]) + target_arch += {'mips': mips_ss} target_softmmu_arch += {'mips': mips_softmmu_ss} |