diff options
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-04-13 10:47:10 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-05-02 16:49:35 +0200 |
| commit | a2b0a27d33e9b1079698cee04ff029a0555b5ea5 (patch) | |
| tree | 25d812498da93beddf8910ce957141066ce30daa /target/mips/internal.h | |
| parent | 5679479b9a1b0dd4772904c3af0d02bb3c9e635f (diff) | |
target/mips: Move TCG source files under tcg/ sub directory
To ease maintenance, move all TCG specific files under the tcg/
sub-directory. Adapt the Meson machinery.
The following prototypes:
- mips_tcg_init()
- mips_cpu_do_unaligned_access()
- mips_cpu_do_transaction_failed()
can now be restricted to the "tcg-internal.h" header.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-29-f4bug@amsat.org>
Diffstat (limited to 'target/mips/internal.h')
| -rw-r--r-- | target/mips/internal.h | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/target/mips/internal.h b/target/mips/internal.h index dd332b4dce..18d5da64a5 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -82,9 +82,6 @@ extern const int mips_defs_number; int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); #define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL) #define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL) @@ -151,12 +148,6 @@ struct CPUMIPSTLBContext { } mmu; }; -void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, - vaddr addr, unsigned size, - MMUAccessType access_type, - int mmu_idx, MemTxAttrs attrs, - MemTxResult response, uintptr_t retaddr); - void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); @@ -209,8 +200,6 @@ static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env) return r; } -void mips_tcg_init(void); - void msa_reset(CPUMIPSState *env); /* cp0_timer.c */ |