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| author | Huacai Chen <zltjiangshi@gmail.com> | 2020-06-02 10:39:15 +0800 |
|---|---|---|
| committer | Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> | 2020-06-09 17:32:45 +0200 |
| commit | af868995e1b7641577300d1342ede452ef0c5565 (patch) | |
| tree | ad3cc1a541f045d6cf0acedc38209043ab3fee7c /target/mips/internal.h | |
| parent | 9579f7816855757c747f9428a8e53d0fe0a0e9b7 (diff) | |
target/mips: Add Loongson-3 CPU definition
Loongson-3 CPU family include Loongson-3A R1/R2/R3/R4 and Loongson-3B
R1/R2. Loongson-3A R1 is the oldest and its ISA is the smallest, while
Loongson-3A R4 is the newest and its ISA is almost the superset of all
others. To reduce complexity, we just define two CPU types:
1) "Loongson-3A1000" CPU which is corresponding to Loongson-3A R1. It is
suitable for TCG because Loongson-3A R1 has fewest ASE.
2) "Loongson-3A4000" CPU which is corresponding to Loongson-3A R4. It is
suitable for KVM because Loongson-3A R4 has the VZ ASE.
Loongson-3A has CONFIG6 and CONFIG7, so add their bit-fields as well.
[AM: Rearranged insn_flags, added comments, renamed lmi_helper.c,
improved commit message, fixed checkpatch warnings]
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <1591065557-9174-3-git-send-email-chenhc@lemote.com>
Diffstat (limited to 'target/mips/internal.h')
| -rw-r--r-- | target/mips/internal.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/mips/internal.h b/target/mips/internal.h index 684356e309..7f159a9230 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -36,7 +36,9 @@ struct mips_def_t { int32_t CP0_Config5; int32_t CP0_Config5_rw_bitmask; int32_t CP0_Config6; + int32_t CP0_Config6_rw_bitmask; int32_t CP0_Config7; + int32_t CP0_Config7_rw_bitmask; target_ulong CP0_LLAddr_rw_bitmask; int CP0_LLAddr_shift; int32_t SYNCI_Step; |