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authorzhaolichang <zhaolichang@huawei.com>2020-10-09 14:44:41 +0800
committerPhilippe Mathieu-Daudé <f4bug@amsat.org>2020-10-17 11:08:42 +0200
commit8cdf88690dc79511cfa1b2557434c09e3685f090 (patch)
tree853b6d1cb9f7d0f986375ca18c8cf60854057446 /target/mips/internal.h
parent5ebc664800b66f886f58cd4d5bcc7785644c9980 (diff)
target/mips: Fix some comment spelling errors
There are many spelling errors in the comments in target/mips/. Use spellcheck to check the spelling errors. Signed-off-by: zhaolichang <zhaolichang@huawei.com> Reviewed-by: David Edmondson <david.edmondson@oracle.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201009064449.2336-7-zhaolichang@huawei.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'target/mips/internal.h')
-rw-r--r--target/mips/internal.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 7f159a9230..b811f547f3 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -188,7 +188,7 @@ static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
/*
* A MIPS configured with a vectorizing external interrupt controller
* will feed a vector into the Cause pending lines. The core treats
- * the status lines as a vector level, not as indiviual masks.
+ * the status lines as a vector level, not as individual masks.
*/
r = pending > status;
} else {