diff options
| author | Alex Bennée <alex.bennee@linaro.org> | 2016-11-14 14:17:28 +0000 |
|---|---|---|
| committer | Alex Bennée <alex.bennee@linaro.org> | 2017-01-13 14:24:37 +0000 |
| commit | d10eb08f5d8389c814b554d01aa2882ac58221bf (patch) | |
| tree | e9b70aa2f4a03e951e2d0d847eacc8adff5de17b /target/mips/helper.c | |
| parent | ba7d3d1858c257e39b47f7f12fa2016ffd960b11 (diff) | |
cputlb: drop flush_global flag from tlb_flush
We have never has the concept of global TLB entries which would avoid
the flush so we never actually use this flag. Drop it and make clear
that tlb_flush is the sledge-hammer it has always been.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
[DG: ppc portions]
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target/mips/helper.c')
| -rw-r--r-- | target/mips/helper.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/target/mips/helper.c b/target/mips/helper.c index c864b15b97..d2e77958fd 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -223,12 +223,12 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical, return ret; } -void cpu_mips_tlb_flush(CPUMIPSState *env, int flush_global) +void cpu_mips_tlb_flush(CPUMIPSState *env) { MIPSCPU *cpu = mips_env_get_cpu(env); /* Flush qemu's TLB and discard all shadowed entries. */ - tlb_flush(CPU(cpu), flush_global); + tlb_flush(CPU(cpu)); env->tlb->tlb_in_use = env->tlb->nb_tlb; } @@ -290,7 +290,7 @@ void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) #if defined(TARGET_MIPS64) if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { /* Access to at least one of the 64-bit segments has been disabled */ - cpu_mips_tlb_flush(env, 1); + cpu_mips_tlb_flush(env); } #endif if (env->CP0_Config3 & (1 << CP0C3_MT)) { |