diff options
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-12-16 12:34:42 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-01-14 17:13:53 +0100 |
| commit | 2e211e0a12e6cde512b65d25799bb3ac25baa371 (patch) | |
| tree | 5f23e2c8af9dec84c6d0c3cc829fc04d65d8ca31 /target/mips/fpu_helper.c | |
| parent | 5f89ce4fc2afdb81eaed90f337d7016207a2b176 (diff) | |
target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6
The MIPS ISA release 6 is common to 32/64-bit CPUs.
To avoid holes in the insn_flags type, update the
definition with the next available bit.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-16-f4bug@amsat.org>
Diffstat (limited to 'target/mips/fpu_helper.c')
| -rw-r--r-- | target/mips/fpu_helper.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index bdb65065ee..91b6a2e11f 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -145,7 +145,7 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt) } break; case 25: - if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) { + if ((env->insn_flags & ISA_MIPS_R6) || (arg1 & 0xffffff00)) { return; } env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | @@ -172,7 +172,7 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt) (env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask)); break; default: - if (env->insn_flags & ISA_MIPS32R6) { + if (env->insn_flags & ISA_MIPS_R6) { do_raise_exception(env, EXCP_RI, GETPC()); } return; |