diff options
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2018-10-16 11:52:35 +0200 |
|---|---|---|
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2018-10-18 20:37:20 +0200 |
| commit | f9c9cd63e3dd84c5f052deec880ec92046bbe305 (patch) | |
| tree | 653ce50b1956e532508445c3fc64b39f27024ae9 /target/mips/cpu.h | |
| parent | 8bacd1ffc702c35d34ccd29b1a20c0273c9759cb (diff) | |
target/mips: Increase 'supported ISAs/ASEs' flag holder size
Increase the size of insn_flags holder size to 64 bits. This is
needed for future extensions since existing bits are almost all used.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Diffstat (limited to 'target/mips/cpu.h')
| -rw-r--r-- | target/mips/cpu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 37703ea011..3b3509ccba 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -811,7 +811,7 @@ struct CPUMIPSState { int CCRes; /* Cycle count resolution/divisor */ uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ - int insn_flags; /* Supported instruction set */ + uint64_t insn_flags; /* Supported instruction set */ /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; |