diff options
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-11-29 23:22:20 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-01-14 17:13:53 +0100 |
| commit | 25a1362875874936c185eba72203de6e9581251e (patch) | |
| tree | ca90a0ba5d60f525cb49d956436b567e94b81bd2 /target/mips/cpu.h | |
| parent | d7efb69382cde8f29cd37df321b399542db9fdd2 (diff) | |
target/mips: Introduce ase_msa_available() helper
Instead of accessing CP0_Config3 directly and checking
the 'MSA Present' bit, introduce an explicit helper,
making the code easier to read.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201208003702.4088927-2-f4bug@amsat.org>
Diffstat (limited to 'target/mips/cpu.h')
| -rw-r--r-- | target/mips/cpu.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 9c45744c5c..b9e227a30e 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1299,6 +1299,12 @@ bool cpu_type_supports_cps_smp(const char *cpu_type); bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask); bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa); +/* Check presence of MSA implementation */ +static inline bool ase_msa_available(CPUMIPSState *env) +{ + return env->CP0_Config3 & (1 << CP0C3_MSAP); +} + /* Check presence of multi-threading ASE implementation */ static inline bool ase_mt_available(CPUMIPSState *env) { |