diff options
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-10-12 11:57:51 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-10-17 11:13:15 +0200 |
| commit | d225b5122029c3d6293aab6e2d0a05597fc92ba4 (patch) | |
| tree | c2f16e1f4469854dd70cace1ade25b293a825e04 /target/mips/cpu.h | |
| parent | 8dadffc01700f79fd66db972fff3a93a594715ee (diff) | |
target/mips: Move cp0_count_ns to CPUMIPSState
Currently the CP0 timer period is fixed at 10 ns, corresponding
to a fixed CPU frequency of 200 MHz (using half the speed of the
CPU).
In few commits we will be able to use a different CPU frequency.
In preparation, move the cp0_count_ns variable to CPUMIPSState
so we can modify it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201012095804.3335117-9-f4bug@amsat.org>
Diffstat (limited to 'target/mips/cpu.h')
| -rw-r--r-- | target/mips/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 7cf7f5239f..085a88e955 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1145,6 +1145,7 @@ struct CPUMIPSState { struct MIPSITUState *itu; MemoryRegion *itc_tag; /* ITC Configuration Tags */ target_ulong exception_base; /* ExceptionBase input to the core */ + uint64_t cp0_count_ns; /* CP0_Count clock period (in nanoseconds) */ }; /** |