diff options
| author | Marcin Nowakowski <marcin.nowakowski@fungible.com> | 2021-05-26 11:35:06 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2022-06-11 11:34:12 +0200 |
| commit | a6bc80f7b11188d86010a2d511498fba2fe4b629 (patch) | |
| tree | ca4799384de1774e3fbd2c2f9ce477d3b616247d /target/mips/cpu.h | |
| parent | 30796f556790631c86c733ab06756981be0e1def (diff) | |
target/mips: Fix WatchHi.M handling
bit 31 (M) of WatchHiN register is a read-only register indicating
whether the next WatchHi register is present. It must not be reset
during user writes to the register.
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@fungible.com>
Reviewed-by: David Daney <david.daney@fungible.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@fungible.com>
Message-Id: <20220511212953.74738-1-philmd@fungible.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'target/mips/cpu.h')
| -rw-r--r-- | target/mips/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 5335ac10a3..6b6b8776d1 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1005,6 +1005,7 @@ typedef struct CPUArchState { */ uint64_t CP0_WatchHi[8]; #define CP0WH_ASID 16 +#define CP0WH_M 31 /* * CP0 Register 20 */ |