diff options
| author | Leon Alrae <leon.alrae@imgtec.com> | 2019-02-11 16:09:23 +0100 |
|---|---|---|
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2019-02-14 17:47:28 +0100 |
| commit | 33a07fa2db66376e6ee780d4a8b064dc5118cf34 (patch) | |
| tree | 67abf3dfc5fb163e7437f697480eeccb489cf536 /target/mips/cpu.h | |
| parent | c7c7e1e9a5e3f0a8a1dbff6e4ccfd21c2dc9f845 (diff) | |
target/mips: reimplement SC instruction emulation and use cmpxchg
Completely rewrite conditional stores handling. Use cmpxchg.
This eliminates need for separate implementations of SC instruction
emulation for user and system emulation.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Emilio G. Cota <cota@braap.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/mips/cpu.h')
| -rw-r--r-- | target/mips/cpu.h | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index f10e016673..eccee375cb 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -876,10 +876,8 @@ struct CPUMIPSState { */ target_ulong lladdr; /* LL virtual address compared against SC */ target_ulong llval; - target_ulong llnewval; uint64_t llval_wp; uint32_t llnewval_wp; - target_ulong llreg; uint64_t CP0_LLAddr_rw_bitmask; int CP0_LLAddr_shift; /* @@ -1156,8 +1154,6 @@ enum { EXCP_LAST = EXCP_TLBRI, }; -/* Dummy exception for conditional stores. */ -#define EXCP_SC 0x100 /* * This is an internally generated WAKE request line. |