diff options
| author | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2019-10-30 13:49:14 +0100 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2020-04-30 12:11:03 +0200 |
| commit | 1ee1bd28fcce858e6f51d2d1d6ef9048bc254b86 (patch) | |
| tree | c61c904430560b9469a17d7a559f6d43e0902db0 /target/microblaze | |
| parent | 648db19685b7030aa558a4ddbd3a8e53d8c9a062 (diff) | |
target/microblaze: Add the opcode-0x0-illegal CPU property
Add the opcode-0x0-illegal CPU property to control if the core
should trap opcode zero as illegal.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'target/microblaze')
| -rw-r--r-- | target/microblaze/cpu.c | 6 | ||||
| -rw-r--r-- | target/microblaze/cpu.h | 1 | ||||
| -rw-r--r-- | target/microblaze/translate.c | 2 |
3 files changed, 7 insertions, 2 deletions
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index c9cf2364ca..418a0cd1fa 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -206,7 +206,9 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) (cpu->cfg.dopb_bus_exception ? PVR2_DOPB_BUS_EXC_MASK : 0) | (cpu->cfg.iopb_bus_exception ? - PVR2_IOPB_BUS_EXC_MASK : 0); + PVR2_IOPB_BUS_EXC_MASK : 0) | + (cpu->cfg.opcode_0_illegal ? + PVR2_OPCODE_0x0_ILL_MASK : 0); env->pvr.regs[5] |= cpu->cfg.dcache_writeback ? PVR5_DCACHE_WRITEBACK_MASK : 0; @@ -274,6 +276,8 @@ static Property mb_properties[] = { /* Enables bus exceptions on failed instruction fetches. */ DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU, cfg.iopb_bus_exception, false), + DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU, + cfg.opcode_0_illegal, false), DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version), DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL), DEFINE_PROP_END_OF_LIST(), diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 1a700a880c..d51587b342 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -303,6 +303,7 @@ struct MicroBlazeCPU { bool endi; bool dopb_bus_exception; bool iopb_bus_exception; + bool opcode_0_illegal; char *version; uint8_t pvr; } cfg; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 37a844db99..222632b670 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1573,7 +1573,7 @@ static inline void decode(DisasContext *dc, uint32_t ir) LOG_DIS("%8.8x\t", dc->ir); if (ir == 0) { - trap_illegal(dc, dc->cpu->env.pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK); + trap_illegal(dc, dc->cpu->cfg.opcode_0_illegal); /* Don't decode nop/zero instructions any further. */ return; } |