diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2020-08-19 22:54:53 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2020-09-01 07:41:38 -0700 |
| commit | dbdb77c4df97205f9fbe1ec10ad35c1cb9729c12 (patch) | |
| tree | 4a49aeb523ab92ee7f147a08ad55d27494868628 /target/microblaze | |
| parent | 39db007eda4310f305fdbc712d59d99284bf11d4 (diff) | |
target/microblaze: Remove cpu_ear
Since cpu_ear is only used during MSR and MTR instructions,
we can just as easily use an explicit load and store, so
eliminate the variable.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/microblaze')
| -rw-r--r-- | target/microblaze/translate.c | 23 |
1 files changed, 15 insertions, 8 deletions
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a862ac4055..f5ca25cead 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -57,7 +57,6 @@ static TCGv_i32 env_debug; static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; -static TCGv_i64 cpu_ear; static TCGv_i32 cpu_esr; static TCGv_i32 env_imm; static TCGv_i32 env_btaken; @@ -533,7 +532,12 @@ static void dec_msr(DisasContext *dc) msr_write(dc, cpu_R[dc->ra]); break; case SR_EAR: - tcg_gen_extu_i32_i64(cpu_ear, cpu_R[dc->ra]); + { + TCGv_i64 t64 = tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(t64, cpu_R[dc->ra]); + tcg_gen_st_i64(t64, cpu_env, offsetof(CPUMBState, ear)); + tcg_temp_free_i64(t64); + } break; case SR_ESR: tcg_gen_mov_i32(cpu_esr, cpu_R[dc->ra]); @@ -573,10 +577,15 @@ static void dec_msr(DisasContext *dc) msr_read(dc, cpu_R[dc->rd]); break; case SR_EAR: - if (extended) { - tcg_gen_extrh_i64_i32(cpu_R[dc->rd], cpu_ear); - } else { - tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_ear); + { + TCGv_i64 t64 = tcg_temp_new_i64(); + tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear)); + if (extended) { + tcg_gen_extrh_i64_i32(cpu_R[dc->rd], t64); + } else { + tcg_gen_extrl_i64_i32(cpu_R[dc->rd], t64); + } + tcg_temp_free_i64(t64); } break; case SR_ESR: @@ -1865,8 +1874,6 @@ void mb_tcg_init(void) tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, pc), "rpc"); cpu_msr = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, msr), "rmsr"); - cpu_ear = - tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); cpu_esr = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr"); } |