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authorRichard Henderson <richard.henderson@linaro.org>2023-06-19 11:08:41 +0200
committerRichard Henderson <richard.henderson@linaro.org>2023-06-26 17:33:00 +0200
commitf6ff4923b92ceefbe5650c3e90ccdcc57dc60fb7 (patch)
treedeaf03b750a4e627c0de3530bcebe6ff61996136 /target/microblaze
parent70bfde9a7de7fa3495d9e2bd7142cb1bc656484e (diff)
target/microblaze: Define TCG_GUEST_DEFAULT_MO
The microblaze architecture does not reorder instructions. While there is an MBAR wait-for-data-access instruction, this concerns synchronizing with DMA. This should have been defined when enabling MTTCG. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com> Fixes: d449561b130 ("configure: microblaze: Enable mttcg") Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/microblaze')
-rw-r--r--target/microblaze/cpu.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 3525de144c..a7b040abd4 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -24,6 +24,9 @@
#include "exec/cpu-defs.h"
#include "qemu/cpu-float.h"
+/* MicroBlaze is always in-order. */
+#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
+
typedef struct CPUArchState CPUMBState;
#if !defined(CONFIG_USER_ONLY)
#include "mmu.h"