diff options
| author | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2018-04-14 23:44:51 +0200 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2018-05-29 09:35:14 +0200 |
| commit | a1b48e3a3aa19d6e03b6c39cae4e915f5cceb028 (patch) | |
| tree | 5f4713d3826dbf01c30dd6605765918fec4c5875 /target/microblaze/translate.c | |
| parent | d248e1beac9a640c033cc7d3c3d494576a74bbc0 (diff) | |
target-microblaze: Implement MFSE EAR
Implement MFSE EAR to enable access to the upper part of EAR.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'target/microblaze/translate.c')
| -rw-r--r-- | target/microblaze/translate.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 504db88890..7475003847 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -459,7 +459,7 @@ static void dec_msr(DisasContext *dc) CPUState *cs = CPU(dc->cpu); TCGv_i32 t0, t1; unsigned int sr, rn; - bool to, clrset; + bool to, clrset, extended; sr = extract32(dc->imm, 0, 14); to = extract32(dc->imm, 14, 1); @@ -467,6 +467,9 @@ static void dec_msr(DisasContext *dc) dc->type_b = 1; if (to) { dc->cpustate_changed = 1; + extended = extract32(dc->imm, 24, 1); + } else { + extended = extract32(dc->imm, 19, 1); } /* msrclr and msrset. */ @@ -559,6 +562,10 @@ static void dec_msr(DisasContext *dc) msr_read(dc, cpu_R[dc->rd]); break; case SR_EAR: + if (extended) { + tcg_gen_extrh_i64_i32(cpu_R[dc->rd], cpu_SR[sr]); + break; + } case SR_ESR: case SR_FSR: case SR_BTR: |