diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2020-04-30 16:47:23 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-04-30 16:47:23 +0100 |
| commit | 27c94566379069fb8930bb1433dcffbf7df3203d (patch) | |
| tree | a9d360e99d9fcb0291987c55ec94e3b0390022f4 /target/microblaze/op_helper.c | |
| parent | 126eeee6c7b516e0a348dd4d60e59dbfa4b4b513 (diff) | |
| parent | 3ed43b5031ed2d7ef501bb81b87caed960218461 (diff) | |
Merge remote-tracking branch 'remotes/edgar/tags/edgar/xilinx-next-2020-04-30.for-upstream' into staging
For upstream
# gpg: Signature made Thu 30 Apr 2020 11:14:13 BST
# gpg: using RSA key AC44FEDC14F7F1EBEDBF415129C596780F6BCA83
# gpg: Good signature from "Edgar E. Iglesias (Xilinx key) <edgar.iglesias@xilinx.com>" [unknown]
# gpg: aka "Edgar E. Iglesias <edgar.iglesias@gmail.com>" [full]
# Primary key fingerprint: AC44 FEDC 14F7 F1EB EDBF 4151 29C5 9678 0F6B CA83
* remotes/edgar/tags/edgar/xilinx-next-2020-04-30.for-upstream:
target/microblaze: Add the pvr-user2 property
target/microblaze: Add the pvr-user1 property
target/microblaze: Add the unaligned-exceptions property
target/microblaze: Add the div-zero-exception property
target/microblaze: Add the ill-opcode-exception property
target/microblaze: Add the opcode-0x0-illegal CPU property
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/microblaze/op_helper.c')
| -rw-r--r-- | target/microblaze/op_helper.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 18677ddfca..f3b17a95b3 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -132,11 +132,12 @@ uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf) static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b) { + MicroBlazeCPU *cpu = env_archcpu(env); + if (b == 0) { env->sregs[SR_MSR] |= MSR_DZ; - if ((env->sregs[SR_MSR] & MSR_EE) - && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) { + if ((env->sregs[SR_MSR] & MSR_EE) && cpu->cfg.div_zero_exception) { env->sregs[SR_ESR] = ESR_EC_DIVZERO; helper_raise_exception(env, EXCP_HW_EXCP); } |