diff options
| author | Joe Komlodi <joe.komlodi@xilinx.com> | 2021-01-21 16:18:53 -0800 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2021-01-27 08:32:55 +0100 |
| commit | ea2ccb65615f8e50d6002c6b0de33691c00aae9d (patch) | |
| tree | 54e2715ebcfa94522f7d3c0a6006f05df9895c00 /target/microblaze/cpu.h | |
| parent | 9cd69f1a270235b652766f00b94114f48a2d603f (diff) | |
target/microblaze: Add use-non-secure property
This property is used to control the security of the following interfaces
on MicroBlaze:
M_AXI_DP - data interface
M_AXI_IP - instruction interface
M_AXI_DC - dcache interface
M_AXI_IC - icache interface
It works by enabling or disabling the use of the non_secure[3:0] signals.
Interfaces and their corresponding values are taken from:
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug984-vivado-microblaze-ref.pdf
page 153.
Signed-off-by: Joe Komlodi <komlodi@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-Id: <1611274735-303873-2-git-send-email-komlodi@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'target/microblaze/cpu.h')
| -rw-r--r-- | target/microblaze/cpu.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index c1c264199f..199cfb02d6 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -233,6 +233,12 @@ typedef struct CPUMBState CPUMBState; #define TARGET_INSN_START_EXTRA_WORDS 1 +/* use-non-secure property masks */ +#define USE_NON_SECURE_M_AXI_DP_MASK 0x1 +#define USE_NON_SECURE_M_AXI_IP_MASK 0x2 +#define USE_NON_SECURE_M_AXI_DC_MASK 0x4 +#define USE_NON_SECURE_M_AXI_IC_MASK 0x8 + struct CPUMBState { uint32_t bvalue; /* TCG temporary, only valid during a TB */ uint32_t btarget; /* Full resolved branch destination */ @@ -316,6 +322,7 @@ typedef struct { bool use_msr_instr; bool use_pcmp_instr; bool use_mmu; + uint8_t use_non_secure; bool dcache_writeback; bool endi; bool dopb_bus_exception; @@ -337,6 +344,10 @@ struct MicroBlazeCPU { CPUState parent_obj; /*< public >*/ + bool ns_axi_dp; + bool ns_axi_ip; + bool ns_axi_dc; + bool ns_axi_ic; CPUNegativeOffsetState neg; CPUMBState env; |