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| author | Kirill A. Shutemov <kirill.shutemov@linux.intel.com> | 2016-12-15 03:13:05 +0300 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2016-12-22 16:01:04 +0100 |
| commit | 6c7c3c21f95dd9af8a0691c0dd29b07247984122 (patch) | |
| tree | ee8ef96cdff2c67cb89aa7217edc106a4bfc2be3 /target/microblaze/cpu-qom.h | |
| parent | c52ab08aee6f7d4717fc6b517174043126bd302f (diff) | |
x86: implement la57 paging mode
The new paging more is extension of IA32e mode with more additional page
table level.
It brings support of 57-bit vitrual address space (128PB) and 52-bit
physical address space (4PB).
The structure of new page table level is identical to pml4.
The feature is enumerated with CPUID.(EAX=07H, ECX=0):ECX[bit 16].
CR4.LA57[bit 12] need to be set when pageing enables to activate 5-level
paging mode.
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Message-Id: <20161215001305.146807-1-kirill.shutemov@linux.intel.com>
[Drop changes to target-i386/translate.c. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target/microblaze/cpu-qom.h')
0 files changed, 0 insertions, 0 deletions