diff options
| author | Laurent Vivier <laurent@vivier.eu> | 2017-06-05 12:00:14 +0200 |
|---|---|---|
| committer | Laurent Vivier <laurent@vivier.eu> | 2017-06-07 11:18:30 +0200 |
| commit | 18059c9e1648bf4fc5c7c1bae6f54690742b05ba (patch) | |
| tree | d9e212d180ca36b175d71633dd08a98a7e50d12a /target/m68k/translate.c | |
| parent | 65dfad62a176f5265f801683be64149c5ad55f7d (diff) | |
target/m68k: implement rtd
Add "Return and Deallocate" (rtd) instruction.
RTD #d
(SP) -> PC
SP + 4 + d -> SP
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Tested-By: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
Message-Id: <20170605100014.22981-1-laurent@vivier.eu>
Diffstat (limited to 'target/m68k/translate.c')
| -rw-r--r-- | target/m68k/translate.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 9f60fbc0db..ad4d4efb8d 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -2483,6 +2483,16 @@ DISAS_INSN(nop) { } +DISAS_INSN(rtd) +{ + TCGv tmp; + int16_t offset = read_im16(env, s); + + tmp = gen_load(s, OS_LONG, QREG_SP, 0); + tcg_gen_addi_i32(QREG_SP, QREG_SP, offset + 4); + gen_jmp(s, tmp); +} + DISAS_INSN(rts) { TCGv tmp; @@ -4904,6 +4914,7 @@ void register_m68k_insns (CPUM68KState *env) BASE(nop, 4e71, ffff); BASE(stop, 4e72, ffff); BASE(rte, 4e73, ffff); + INSN(rtd, 4e74, ffff, RTD); BASE(rts, 4e75, ffff); INSN(movec, 4e7b, ffff, CF_ISA_A); BASE(jump, 4e80, ffc0); |