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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-03-12 18:56:56 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-03-12 18:56:56 +0000 |
| commit | 8e6bc6cdc82d45f203bc9fc4342c0452214c74fe (patch) | |
| tree | 04bfff6f6d509d0d3e63e2d7eecc9529fd20d9b3 /target/m68k/translate.c | |
| parent | 3f8d1885e48e4d72eab0688f604de62e0aea7a38 (diff) | |
| parent | a9431a03f70c8c711a870d4c1a0439bdbb4703cf (diff) | |
Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-6.0-pull-request' into staging
Prepare MacOS ROM support:
- add RTR instruction
- fix unaligned access requirement
- fix ATC bit (68040 MMU)
# gpg: Signature made Thu 11 Mar 2021 22:18:11 GMT
# gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C
# gpg: issuer "laurent@vivier.eu"
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full]
# gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full]
# gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full]
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C
* remotes/vivier/tags/m68k-for-6.0-pull-request:
target/m68k: add M68K_FEATURE_UNALIGNED_DATA feature
target/m68k: reformat m68k_features enum
target/m68k: don't set SSW ATC bit for physical bus errors
target/m68k: implement rtr instruction
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/m68k/translate.c')
| -rw-r--r-- | target/m68k/translate.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/target/m68k/translate.c b/target/m68k/translate.c index ac936ebe8f..200018ae6a 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -2969,6 +2969,25 @@ DISAS_INSN(rtd) gen_jmp(s, tmp); } +DISAS_INSN(rtr) +{ + TCGv tmp; + TCGv ccr; + TCGv sp; + + sp = tcg_temp_new(); + ccr = gen_load(s, OS_WORD, QREG_SP, 0, IS_USER(s)); + tcg_gen_addi_i32(sp, QREG_SP, 2); + tmp = gen_load(s, OS_LONG, sp, 0, IS_USER(s)); + tcg_gen_addi_i32(QREG_SP, sp, 4); + tcg_temp_free(sp); + + gen_set_sr(s, ccr, true); + tcg_temp_free(ccr); + + gen_jmp(s, tmp); +} + DISAS_INSN(rts) { TCGv tmp; @@ -6015,6 +6034,7 @@ void register_m68k_insns (CPUM68KState *env) BASE(nop, 4e71, ffff); INSN(rtd, 4e74, ffff, RTD); BASE(rts, 4e75, ffff); + INSN(rtr, 4e77, ffff, M68000); BASE(jump, 4e80, ffc0); BASE(jump, 4ec0, ffc0); INSN(addsubq, 5000, f080, M68000); |