diff options
author | Song Gao <gaosong@loongson.cn> | 2023-09-14 10:26:30 +0800 |
---|---|---|
committer | Song Gao <gaosong@loongson.cn> | 2023-09-20 14:33:41 +0800 |
commit | 12ad133f20b621f34dc737b821197ee8543c751e (patch) | |
tree | 31a13fd53ab7fe201529ec45871f4f9ebaf45476 /target/loongarch | |
parent | 77fca79428677d2b834632cd83a24ff28a3d91ce (diff) |
target/loongarch: Implement xvclo xvclz
This patch includes:
- XVCLO.{B/H/W/D};
- XVCLZ.{B/H/W/D}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230914022645.1151356-43-gaosong@loongson.cn>
Diffstat (limited to 'target/loongarch')
-rw-r--r-- | target/loongarch/disas.c | 9 | ||||
-rw-r--r-- | target/loongarch/insn_trans/trans_vec.c.inc | 8 | ||||
-rw-r--r-- | target/loongarch/insns.decode | 9 | ||||
-rw-r--r-- | target/loongarch/vec_helper.c | 3 |
4 files changed, 28 insertions, 1 deletions
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c index 421eecbb71..bbf530b349 100644 --- a/target/loongarch/disas.c +++ b/target/loongarch/disas.c @@ -2196,6 +2196,15 @@ INSN_LASX(xvssrarni_hu_w, vv_i) INSN_LASX(xvssrarni_wu_d, vv_i) INSN_LASX(xvssrarni_du_q, vv_i) +INSN_LASX(xvclo_b, vv) +INSN_LASX(xvclo_h, vv) +INSN_LASX(xvclo_w, vv) +INSN_LASX(xvclo_d, vv) +INSN_LASX(xvclz_b, vv) +INSN_LASX(xvclz_h, vv) +INSN_LASX(xvclz_w, vv) +INSN_LASX(xvclz_d, vv) + INSN_LASX(xvreplgr2vr_b, vr) INSN_LASX(xvreplgr2vr_h, vr) INSN_LASX(xvreplgr2vr_w, vr) diff --git a/target/loongarch/insn_trans/trans_vec.c.inc b/target/loongarch/insn_trans/trans_vec.c.inc index 817d503490..85d0d10355 100644 --- a/target/loongarch/insn_trans/trans_vec.c.inc +++ b/target/loongarch/insn_trans/trans_vec.c.inc @@ -3949,6 +3949,14 @@ TRANS(vclz_b, LSX, gen_vv, gen_helper_vclz_b) TRANS(vclz_h, LSX, gen_vv, gen_helper_vclz_h) TRANS(vclz_w, LSX, gen_vv, gen_helper_vclz_w) TRANS(vclz_d, LSX, gen_vv, gen_helper_vclz_d) +TRANS(xvclo_b, LASX, gen_xx, gen_helper_vclo_b) +TRANS(xvclo_h, LASX, gen_xx, gen_helper_vclo_h) +TRANS(xvclo_w, LASX, gen_xx, gen_helper_vclo_w) +TRANS(xvclo_d, LASX, gen_xx, gen_helper_vclo_d) +TRANS(xvclz_b, LASX, gen_xx, gen_helper_vclz_b) +TRANS(xvclz_h, LASX, gen_xx, gen_helper_vclz_h) +TRANS(xvclz_w, LASX, gen_xx, gen_helper_vclz_w) +TRANS(xvclz_d, LASX, gen_xx, gen_helper_vclz_d) TRANS(vpcnt_b, LSX, gen_vv, gen_helper_vpcnt_b) TRANS(vpcnt_h, LSX, gen_vv, gen_helper_vpcnt_h) diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode index dc74bae7a5..3175532045 100644 --- a/target/loongarch/insns.decode +++ b/target/loongarch/insns.decode @@ -1770,6 +1770,15 @@ xvssrarni_hu_w 0111 01110110 11001 ..... ..... ..... @vv_ui5 xvssrarni_wu_d 0111 01110110 1101 ...... ..... ..... @vv_ui6 xvssrarni_du_q 0111 01110110 111 ....... ..... ..... @vv_ui7 +xvclo_b 0111 01101001 11000 00000 ..... ..... @vv +xvclo_h 0111 01101001 11000 00001 ..... ..... @vv +xvclo_w 0111 01101001 11000 00010 ..... ..... @vv +xvclo_d 0111 01101001 11000 00011 ..... ..... @vv +xvclz_b 0111 01101001 11000 00100 ..... ..... @vv +xvclz_h 0111 01101001 11000 00101 ..... ..... @vv +xvclz_w 0111 01101001 11000 00110 ..... ..... @vv +xvclz_d 0111 01101001 11000 00111 ..... ..... @vv + xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr diff --git a/target/loongarch/vec_helper.c b/target/loongarch/vec_helper.c index 68f3667ef4..363309b6ea 100644 --- a/target/loongarch/vec_helper.c +++ b/target/loongarch/vec_helper.c @@ -2264,8 +2264,9 @@ void HELPER(NAME)(void *vd, void *vj, uint32_t desc) \ int i; \ VReg *Vd = (VReg *)vd; \ VReg *Vj = (VReg *)vj; \ + int oprsz = simd_oprsz(desc); \ \ - for (i = 0; i < LSX_LEN/BIT; i++) \ + for (i = 0; i < oprsz / (BIT / 8); i++) \ { \ Vd->E(i) = DO_OP(Vj->E(i)); \ } \ |