diff options
| author | Xiaojuan Yang <yangxiaojuan@loongson.cn> | 2022-06-06 20:43:19 +0800 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2022-06-06 18:09:03 +0000 |
| commit | f9bf50745f29c85e531857898ed7927b6db7c763 (patch) | |
| tree | 7cbc8cceef002562c51547da9382d6a16dd8a384 /target/loongarch/translate.c | |
| parent | d2cba6f7cea9d55aa0567fa8efdeaf2028e1de5e (diff) | |
target/loongarch: Add timer related instructions support.
This includes:
-RDTIME{L/H}.W
-RDTIME.D
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-30-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/loongarch/translate.c')
| -rw-r--r-- | target/loongarch/translate.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index 0f098924a3..c9afd11420 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -25,6 +25,8 @@ static TCGv cpu_lladdr, cpu_llval; TCGv_i32 cpu_fcsr0; TCGv_i64 cpu_fpr[32]; +#include "exec/gen-icount.h" + #define DISAS_STOP DISAS_TARGET_0 #define DISAS_EXIT DISAS_TARGET_1 #define DISAS_EXIT_UPDATE DISAS_TARGET_2 |