diff options
| author | Song Gao <gaosong@loongson.cn> | 2023-05-04 20:28:07 +0800 |
|---|---|---|
| committer | Song Gao <gaosong@loongson.cn> | 2023-05-06 11:19:49 +0800 |
| commit | 843b627a395a8f6cda8a717c5c8b081358b9d711 (patch) | |
| tree | 2b8dd139640cc8873dc8d9aedb170dee4b5357dc /target/loongarch/insns.decode | |
| parent | e93dd43147351290ec1eac83e04cfc0a7f641d63 (diff) | |
target/loongarch: Implement vld vst
This patch includes:
- VLD[X], VST[X];
- VLDREPL.{B/H/W/D};
- VSTELM.{B/H/W/D}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-42-gaosong@loongson.cn>
Diffstat (limited to 'target/loongarch/insns.decode')
| -rw-r--r-- | target/loongarch/insns.decode | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode index 0263bce28e..ea6eedb7a9 100644 --- a/target/loongarch/insns.decode +++ b/target/loongarch/insns.decode @@ -487,6 +487,17 @@ idle 0000 01100100 10001 ............... @i15 dbcl 0000 00000010 10101 ............... @i15 # +# LSX Fields +# + +%i9s3 10:s9 !function=shl_3 +%i10s2 10:s10 !function=shl_2 +%i11s1 10:s11 !function=shl_1 +%i8s3 10:s8 !function=shl_3 +%i8s2 10:s8 !function=shl_2 +%i8s1 10:s8 !function=shl_1 + +# # LSX Argument sets # @@ -500,6 +511,8 @@ dbcl 0000 00000010 10101 ............... @i15 &rv_i rd vj imm &vr vd rj &vvr vd vj rk +&vrr vd rj rk +&vr_ii vd rj imm imm2 # # LSX Formats @@ -528,6 +541,15 @@ dbcl 0000 00000010 10101 ............... @i15 @rv_ui1 .... ........ ..... .... imm:1 vj:5 rd:5 &rv_i @vr .... ........ ..... ..... rj:5 vd:5 &vr @vvr .... ........ ..... rk:5 vj:5 vd:5 &vvr +@vr_i9 .... ........ . ......... rj:5 vd:5 &vr_i imm=%i9s3 +@vr_i10 .... ........ .......... rj:5 vd:5 &vr_i imm=%i10s2 +@vr_i11 .... ....... ........... rj:5 vd:5 &vr_i imm=%i11s1 +@vr_i12 .... ...... imm:s12 rj:5 vd:5 &vr_i +@vr_i8i1 .... ........ . imm2:1 ........ rj:5 vd:5 &vr_ii imm=%i8s3 +@vr_i8i2 .... ........ imm2:2 ........ rj:5 vd:5 &vr_ii imm=%i8s2 +@vr_i8i3 .... ....... imm2:3 ........ rj:5 vd:5 &vr_ii imm=%i8s1 +@vr_i8i4 .... ...... imm2:4 imm:s8 rj:5 vd:5 &vr_ii +@vrr .... ........ ..... rk:5 rj:5 vd:5 &vrr vadd_b 0111 00000000 10100 ..... ..... ..... @vvv vadd_h 0111 00000000 10101 ..... ..... ..... @vvv @@ -1256,3 +1278,17 @@ vextrins_d 0111 00111000 00 ........ ..... ..... @vv_ui8 vextrins_w 0111 00111000 01 ........ ..... ..... @vv_ui8 vextrins_h 0111 00111000 10 ........ ..... ..... @vv_ui8 vextrins_b 0111 00111000 11 ........ ..... ..... @vv_ui8 + +vld 0010 110000 ............ ..... ..... @vr_i12 +vst 0010 110001 ............ ..... ..... @vr_i12 +vldx 0011 10000100 00000 ..... ..... ..... @vrr +vstx 0011 10000100 01000 ..... ..... ..... @vrr + +vldrepl_d 0011 00000001 0 ......... ..... ..... @vr_i9 +vldrepl_w 0011 00000010 .......... ..... ..... @vr_i10 +vldrepl_h 0011 0000010 ........... ..... ..... @vr_i11 +vldrepl_b 0011 000010 ............ ..... ..... @vr_i12 +vstelm_d 0011 00010001 0 . ........ ..... ..... @vr_i8i1 +vstelm_w 0011 00010010 .. ........ ..... ..... @vr_i8i2 +vstelm_h 0011 0001010 ... ........ ..... ..... @vr_i8i3 +vstelm_b 0011 000110 .... ........ ..... ..... @vr_i8i4 |