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authorRui Wang <wangrui@loongson.cn>2022-11-04 12:05:16 +0800
committerSong Gao <gaosong@loongson.cn>2022-11-04 17:10:52 +0800
commitb4bda2006f482f778d9dbf86038ff115fe89db92 (patch)
tree0aede78e9c1b850185cca8bd59ce3b2156834238 /target/loongarch/insn_trans
parent8752b1306002237c39b3f849ca564c9db55c8b1f (diff)
target/loongarch: Adjust the layout of hardware flags bit fields
Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Rui Wang <wangrui@loongson.cn> Message-Id: <20221104040517.222059-2-wangrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
Diffstat (limited to 'target/loongarch/insn_trans')
-rw-r--r--target/loongarch/insn_trans/trans_privileged.c.inc2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/loongarch/insn_trans/trans_privileged.c.inc b/target/loongarch/insn_trans/trans_privileged.c.inc
index 9c4dcbfcfb..ff3a6d95ae 100644
--- a/target/loongarch/insn_trans/trans_privileged.c.inc
+++ b/target/loongarch/insn_trans/trans_privileged.c.inc
@@ -159,7 +159,7 @@ static const CSRInfo csr_info[] = {
static bool check_plv(DisasContext *ctx)
{
- if (ctx->base.tb->flags == MMU_USER_IDX) {
+ if (ctx->mem_idx == MMU_USER_IDX) {
generate_exception(ctx, EXCCODE_IPE);
return true;
}