diff options
| author | Paolo Bonzini <pbonzini@redhat.com> | 2024-05-25 10:03:22 +0200 |
|---|---|---|
| committer | Michael Tokarev <mjt@tls.msk.ru> | 2024-05-27 07:30:35 +0300 |
| commit | f417712ef156235b96c2c15a1ad7e3dfe5542695 (patch) | |
| tree | b131e1c3402cc07ee4a136a8ab7d3257d2247957 /target/i386 | |
| parent | 9abcd968e77f257abedb327eb3109ec30a0ba9a7 (diff) | |
target/i386: no single-step exception after MOV or POP SS
Intel SDM 18.3.1.4 "If an occurrence of the MOV or POP instruction
loads the SS register executes with EFLAGS.TF = 1, no single-step debug
exception occurs following the MOV or POP instruction."
Cc: qemu-stable@nongnu.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
(cherry picked from commit f0f0136abba688a6516647a79cc91e03fad6d5d7)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
(Mjt: context fixup for v8.1.0-1189-gad75a51e84af "tcg: Rename cpu_env to tcg_env")
Diffstat (limited to 'target/i386')
| -rw-r--r-- | target/i386/tcg/translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index b4f25e2f59..417bc26e8f 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2833,7 +2833,7 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, bool jr) if (recheck_tf) { gen_helper_rechecking_single_step(cpu_env); tcg_gen_exit_tb(NULL, 0); - } else if (s->flags & HF_TF_MASK) { + } else if ((s->flags & HF_TF_MASK) && !inhibit) { gen_helper_single_step(cpu_env); } else if (jr && /* give irqs a chance to happen */ |