diff options
| author | Lluís Vilanova <vilanova@ac.upc.edu> | 2017-07-14 11:37:46 +0300 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2017-09-06 08:06:47 -0700 |
| commit | 9d75f52b34053066b8e8fc37610d5f300d67538b (patch) | |
| tree | 37b49043e38ed19997fa143c9c9576713f617edd /target/i386 | |
| parent | 9761d39b09c4beb1340bf3074be3d3e0a5d453a4 (diff) | |
target/i386: [tcg] Port to insn_start
Incrementally paves the way towards using the generic instruction translation
loop.
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Alex Benneé <alex.benee@linaro.org>
Message-Id: <150002146647.22386.13380064201042141261.stgit@frigg.lan>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target/i386')
| -rw-r--r-- | target/i386/translate.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/target/i386/translate.c b/target/i386/translate.c index 4281e9bc56..b7e5854513 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8449,6 +8449,13 @@ static int i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu, return max_insns; } +static void i386_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + + tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -8476,7 +8483,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) num_insns = 0; gen_tb_start(tb); for(;;) { - tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); + i386_tr_insn_start(&dc->base, cs); num_insns++; /* If RF is set, suppress an internally generated breakpoint. */ |