diff options
| author | Paolo Bonzini <pbonzini@redhat.com> | 2022-03-24 09:08:39 +0100 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2022-03-24 09:11:03 +0100 |
| commit | de65b39a517c9977769c612af716dc418ce2ea0b (patch) | |
| tree | a98cfc64dc1230134c98f9cf3f4b09d696f25cbb /target/i386 | |
| parent | 98a02bc4492c7e00a703ad42f1ff9d2f3521a138 (diff) | |
target/i386: tcg: high bits SSE cmp operation must be ignored
High bits in the immediate operand of SSE comparisons are ignored, they
do not result in an undefined opcode exception. This is mentioned
explicitly in the Intel documentation.
Reported-by: sonicadvance1@gmail.com
Closes: https://gitlab.com/qemu-project/qemu/-/issues/184
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target/i386')
| -rw-r--r-- | target/i386/tcg/translate.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 2a94d33742..c393913fe0 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -4509,10 +4509,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, sse_fn_ppi(s->ptr0, s->ptr1, tcg_const_i32(val)); break; case 0xc2: - /* compare insns */ - val = x86_ldub_code(env, s); - if (val >= 8) - goto unknown_op; + /* compare insns, bits 7:3 (7:5 for AVX) are ignored */ + val = x86_ldub_code(env, s) & 7; sse_fn_epp = sse_op_table4[val][b1]; tcg_gen_addi_ptr(s->ptr0, cpu_env, op1_offset); |