diff options
| author | Paolo Bonzini <pbonzini@redhat.com> | 2020-06-26 05:53:36 -0400 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2020-07-10 18:02:22 -0400 |
| commit | c0c8445255b2b5b440c355431c8b01b7b7b7c8cf (patch) | |
| tree | b591227a4b9c015ad804c6e0f7fdfcb3d9403aeb /target/i386/translate.c | |
| parent | 6c9cce1ff348709869262e4bd15ad4fedf513f17 (diff) | |
target/i386: implement undocumented "smsw r32" behavior
In 32-bit mode, the higher 16 bits of the destination
register are undefined. In practice CR0[31:0] is stored,
just like in 64-bit mode, so just remove the "if" that
currently differentiates the behavior.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reported-by: Roman Bolshakov <r.bolshakov@yadro.com>
Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target/i386/translate.c')
| -rw-r--r-- | target/i386/translate.c | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/target/i386/translate.c b/target/i386/translate.c index 5ef72ff401..a1d31f09c1 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -7579,12 +7579,13 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) CASE_MODRM_OP(4): /* smsw */ gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0); tcg_gen_ld_tl(s->T0, cpu_env, offsetof(CPUX86State, cr[0])); - if (CODE64(s)) { - mod = (modrm >> 6) & 3; - ot = (mod != 3 ? MO_16 : s->dflag); - } else { - ot = MO_16; - } + /* + * In 32-bit mode, the higher 16 bits of the destination + * register are undefined. In practice CR0[31:0] is stored + * just like in 64-bit mode. + */ + mod = (modrm >> 6) & 3; + ot = (mod != 3 ? MO_16 : s->dflag); gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); break; case 0xee: /* rdpkru */ |