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| author | Peter Maydell <peter.maydell@linaro.org> | 2022-02-21 17:24:05 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-02-21 17:24:05 +0000 |
| commit | 922268067fe4181d6edcfccd689e908e4d1243ad (patch) | |
| tree | b2d27104b2a6533a8d3d02e76e8ccadf0975017a /target/i386/tcg/translate.c | |
| parent | 477c3b934a47adf7de285863f59d6e4503dd1a6d (diff) | |
| parent | 5dc4618e781f36c4bea1b0cdd1bea75b48640c5a (diff) | |
Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging
* More Meson conversions (0.59.x now required rather than suggested)
* UMIP support for TCG x86
* Fix migration crash
* Restore error output for check-block
# gpg: Signature made Mon 21 Feb 2022 09:35:59 GMT
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* remotes/bonzini-gitlab/tags/for-upstream: (29 commits)
configure, meson: move CONFIG_IASL to a Meson option
meson, configure: move ntddscsi API check to meson
meson: require dynamic linking for VSS support
qga/vss-win32: require widl/midl, remove pre-built TLB file
meson: do not make qga/vss-win32/meson.build conditional on C++ presence
configure, meson: replace VSS SDK checks and options with --enable-vss-sdk
qga/vss: use standard windows headers location
qga/vss-win32: use widl if available
meson: drop --with-win-sdk
qga/vss-win32: fix midl arguments
meson: refine check for whether to look for virglrenderer
configure, meson: move guest-agent, tools to meson
configure, meson: move smbd options to meson_options.txt
configure, meson: move coroutine options to meson_options.txt
configure, meson: move some default-disabled options to meson_options.txt
meson: define qemu_cflags/qemu_ldflags
configure, meson: move block layer options to meson_options.txt
configure, meson: move image format options to meson_options.txt
configure, meson: cleanup qemu-ga libraries
configure, meson: move TPM check to meson
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/i386/tcg/translate.c')
| -rw-r--r-- | target/i386/tcg/translate.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 77878cd832..2a94d33742 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -7382,6 +7382,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0: /* sldt */ if (!PE(s) || VM86(s)) goto illegal_op; + if (s->flags & HF_UMIP_MASK && !check_cpl0(s)) { + break; + } gen_svm_check_intercept(s, SVM_EXIT_LDTR_READ); tcg_gen_ld32u_tl(s->T0, cpu_env, offsetof(CPUX86State, ldt.selector)); @@ -7401,6 +7404,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 1: /* str */ if (!PE(s) || VM86(s)) goto illegal_op; + if (s->flags & HF_UMIP_MASK && !check_cpl0(s)) { + break; + } gen_svm_check_intercept(s, SVM_EXIT_TR_READ); tcg_gen_ld32u_tl(s->T0, cpu_env, offsetof(CPUX86State, tr.selector)); @@ -7439,6 +7445,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) modrm = x86_ldub_code(env, s); switch (modrm) { CASE_MODRM_MEM_OP(0): /* sgdt */ + if (s->flags & HF_UMIP_MASK && !check_cpl0(s)) { + break; + } gen_svm_check_intercept(s, SVM_EXIT_GDTR_READ); gen_lea_modrm(env, s, modrm); tcg_gen_ld32u_tl(s->T0, @@ -7495,6 +7504,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; CASE_MODRM_MEM_OP(1): /* sidt */ + if (s->flags & HF_UMIP_MASK && !check_cpl0(s)) { + break; + } gen_svm_check_intercept(s, SVM_EXIT_IDTR_READ); gen_lea_modrm(env, s, modrm); tcg_gen_ld32u_tl(s->T0, cpu_env, offsetof(CPUX86State, idt.limit)); @@ -7670,6 +7682,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; CASE_MODRM_OP(4): /* smsw */ + if (s->flags & HF_UMIP_MASK && !check_cpl0(s)) { + break; + } gen_svm_check_intercept(s, SVM_EXIT_READ_CR0); tcg_gen_ld_tl(s->T0, cpu_env, offsetof(CPUX86State, cr[0])); /* |