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authorPaolo Bonzini <pbonzini@redhat.com>2020-01-20 19:21:43 +0100
committerPaolo Bonzini <pbonzini@redhat.com>2020-01-24 20:59:09 +0100
commit4e45aff398cd1542c2a384a2a3b8600f23337d86 (patch)
tree1f17078d6deb971b2bfea955985a1cc39d1a2bc9 /target/i386/misc_helper.c
parent420ae1fc51c99abfd03b1c590f55617edd2a2bed (diff)
target/i386: add a ucode-rev property
Add the property and plumb it in TCG and HVF (the latter of which tried to support returning a constant value but used the wrong MSR). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1579544504-3616-3-git-send-email-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target/i386/misc_helper.c')
-rw-r--r--target/i386/misc_helper.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/target/i386/misc_helper.c b/target/i386/misc_helper.c
index 3eff6885f8..aed16fe3f0 100644
--- a/target/i386/misc_helper.c
+++ b/target/i386/misc_helper.c
@@ -229,6 +229,7 @@ void helper_rdmsr(CPUX86State *env)
#else
void helper_wrmsr(CPUX86State *env)
{
+ X86CPU *x86_cpu = env_archcpu(env);
uint64_t val;
cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1, GETPC());
@@ -371,6 +372,9 @@ void helper_wrmsr(CPUX86State *env)
env->msr_bndcfgs = val;
cpu_sync_bndcs_hflags(env);
break;
+ case MSR_IA32_UCODE_REV:
+ val = x86_cpu->ucode_rev;
+ break;
default:
if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
&& (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +