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authorPaolo Bonzini <pbonzini@redhat.com>2018-12-20 13:10:40 +0100
committerPaolo Bonzini <pbonzini@redhat.com>2019-02-05 16:50:17 +0100
commitc29b48db1db562caf5076a429747247dcecc3b08 (patch)
tree2198c9aad624f90cd6748edb8f95d239ca5db554 /target/i386/hvf/x86_cpuid.c
parent712f807e1965c8f1f1da5bbec2b92a8c540e6631 (diff)
target-i386: hvf: remove MPX support
MPX support is being phased out by Intel and actually I am not sure that OS X has ever enabled it in XCR0. Drop it from the Hypervisor.framework acceleration. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target/i386/hvf/x86_cpuid.c')
-rw-r--r--target/i386/hvf/x86_cpuid.c18
1 files changed, 1 insertions, 17 deletions
diff --git a/target/i386/hvf/x86_cpuid.c b/target/i386/hvf/x86_cpuid.c
index 9874a46e92..4d957fe896 100644
--- a/target/i386/hvf/x86_cpuid.c
+++ b/target/i386/hvf/x86_cpuid.c
@@ -38,16 +38,6 @@ static uint64_t xgetbv(uint32_t xcr)
return (((uint64_t)edx) << 32) | eax;
}
-static bool vmx_mpx_supported()
-{
- uint64_t cap_exit, cap_entry;
-
- hv_vmx_read_capability(HV_VMX_CAP_ENTRY, &cap_entry);
- hv_vmx_read_capability(HV_VMX_CAP_EXIT, &cap_exit);
-
- return ((cap_exit & (1 << 23)) && (cap_entry & (1 << 16)));
-}
-
uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_t idx,
int reg)
{
@@ -92,11 +82,8 @@ uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_t idx,
CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB |
CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_SHA_NI |
CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL |
- CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_MPX;
+ CPUID_7_0_EBX_INVPCID;
- if (!vmx_mpx_supported()) {
- ebx &= ~CPUID_7_0_EBX_MPX;
- }
hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, &cap);
if (!(cap & CPU_BASED2_INVPCID)) {
ebx &= ~CPUID_7_0_EBX_INVPCID;
@@ -119,9 +106,6 @@ uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_t idx,
XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK |
XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK);
eax &= supp_xcr0;
- if (!vmx_mpx_supported()) {
- eax &= ~(XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK);
- }
} else if (idx == 1) {
hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, &cap);
eax &= CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1;