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| author | Peter Maydell <peter.maydell@linaro.org> | 2022-02-21 17:24:05 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-02-21 17:24:05 +0000 |
| commit | 922268067fe4181d6edcfccd689e908e4d1243ad (patch) | |
| tree | b2d27104b2a6533a8d3d02e76e8ccadf0975017a /target/i386/cpu.h | |
| parent | 477c3b934a47adf7de285863f59d6e4503dd1a6d (diff) | |
| parent | 5dc4618e781f36c4bea1b0cdd1bea75b48640c5a (diff) | |
Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging
* More Meson conversions (0.59.x now required rather than suggested)
* UMIP support for TCG x86
* Fix migration crash
* Restore error output for check-block
# gpg: Signature made Mon 21 Feb 2022 09:35:59 GMT
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* remotes/bonzini-gitlab/tags/for-upstream: (29 commits)
configure, meson: move CONFIG_IASL to a Meson option
meson, configure: move ntddscsi API check to meson
meson: require dynamic linking for VSS support
qga/vss-win32: require widl/midl, remove pre-built TLB file
meson: do not make qga/vss-win32/meson.build conditional on C++ presence
configure, meson: replace VSS SDK checks and options with --enable-vss-sdk
qga/vss: use standard windows headers location
qga/vss-win32: use widl if available
meson: drop --with-win-sdk
qga/vss-win32: fix midl arguments
meson: refine check for whether to look for virglrenderer
configure, meson: move guest-agent, tools to meson
configure, meson: move smbd options to meson_options.txt
configure, meson: move coroutine options to meson_options.txt
configure, meson: move some default-disabled options to meson_options.txt
meson: define qemu_cflags/qemu_ldflags
configure, meson: move block layer options to meson_options.txt
configure, meson: move image format options to meson_options.txt
configure, meson: cleanup qemu-ga libraries
configure, meson: move TPM check to meson
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/i386/cpu.h')
| -rw-r--r-- | target/i386/cpu.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 9911d7c871..e69ab5dd78 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -167,6 +167,7 @@ typedef enum X86Seg { #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */ #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */ #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */ +#define HF_UMIP_SHIFT 27 /* CR4.UMIP */ #define HF_CPL_MASK (3 << HF_CPL_SHIFT) #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) @@ -192,6 +193,7 @@ typedef enum X86Seg { #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT) #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT) #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT) +#define HF_UMIP_MASK (1 << HF_UMIP_SHIFT) /* hflags2 */ @@ -258,7 +260,7 @@ typedef enum X86Seg { (~(target_ulong)(CR4_VME_MASK | CR4_PVI_MASK | CR4_TSD_MASK \ | CR4_DE_MASK | CR4_PSE_MASK | CR4_PAE_MASK \ | CR4_MCE_MASK | CR4_PGE_MASK | CR4_PCE_MASK \ - | CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK |CR4_UMIP_MASK \ + | CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK | CR4_UMIP_MASK \ | CR4_LA57_MASK \ | CR4_FSGSBASE_MASK | CR4_PCIDE_MASK | CR4_OSXSAVE_MASK \ | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_MASK)) |