diff options
| author | Like Xu <like.xu@linux.intel.com> | 2019-06-20 13:45:23 +0800 |
|---|---|---|
| committer | Eduardo Habkost <ehabkost@redhat.com> | 2019-07-05 17:08:04 -0300 |
| commit | a94e1428991f741e2c6636e7c8df7f8d1905d983 (patch) | |
| tree | f09158d8e90fc8ee9c5dcf9aad90902fc57e6fa4 /target/i386/cpu.h | |
| parent | 1c809535e3083d4299899e9843a3f4e44b191a9c (diff) | |
target/i386: Add CPUID.1F generation support for multi-dies PCMachine
The CPUID.1F as Intel V2 Extended Topology Enumeration Leaf would be
exposed if guests want to emulate multiple software-visible die within
each package. Per Intel's SDM, the 0x1f is a superset of 0xb, thus they
can be generated by almost same code as 0xb except die_offset setting.
If the number of dies per package is greater than 1, the cpuid_min_level
would be adjusted to 0x1f regardless of whether the host supports CPUID.1F.
Likewise, the CPUID.1F wouldn't be exposed if env->nr_dies < 2.
Suggested-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Like Xu <like.xu@linux.intel.com>
Message-Id: <20190620054525.37188-2-like.xu@linux.intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Diffstat (limited to 'target/i386/cpu.h')
| -rw-r--r-- | target/i386/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 85319f4ae1..0a96c78669 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -736,6 +736,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) +#define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8) /* MSR Feature Bits */ #define MSR_ARCH_CAP_RDCL_NO (1U << 0) |