diff options
| author | Sebastian Andrzej Siewior <bigeasy@linutronix.de> | 2019-09-25 23:49:48 +0200 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2019-10-04 18:49:17 +0200 |
| commit | e900135dcfb676a4019dc206395e02db5d1de0d6 (patch) | |
| tree | 11eac751d1c9824e49c0ede3034e5c95ade8153a /target/i386/cpu.h | |
| parent | 6f89ec7442ef4a7c7a826ab0809c5583f75de4bf (diff) | |
i386: Add CPUID bit for CLZERO and XSAVEERPTR
The CPUID bits CLZERO and XSAVEERPTR are availble on AMD's ZEN platform
and could be passed to the guest.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target/i386/cpu.h')
| -rw-r--r-- | target/i386/cpu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 5f6e3a029a..87f4afbfd6 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -695,6 +695,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) /* AVX512 BFloat16 Instruction */ +#define CPUID_8000_0008_EBX_CLZERO (1U << 0) /* CLZERO instruction */ +#define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2) /* Always save/restore FP error pointers */ #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) /* Write back and do not invalidate cache */ #define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */ |