aboutsummaryrefslogtreecommitdiff
path: root/target/i386/cpu.h
diff options
context:
space:
mode:
authorBabu Moger <babu.moger@amd.com>2018-05-10 15:41:42 -0500
committerEduardo Habkost <ehabkost@redhat.com>2018-05-15 11:33:33 -0300
commit6aaeb05492ef668f415324f43e7d875c0f1e90b3 (patch)
tree11cf2cc1bdcf6a6ad46770d0b887e8abf81fdcd3 /target/i386/cpu.h
parent7e3482f824809e1f6ffeb5bb8103ba27a7d1a52a (diff)
i386: Add cache information in X86CPUDefinition
Add cache information in X86CPUDefinition and CPUX86State. Signed-off-by: Babu Moger <babu.moger@amd.com> Tested-by: Geoffrey McRae <geoff@hostfission.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20180510204148.11687-3-babu.moger@amd.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Diffstat (limited to 'target/i386/cpu.h')
-rw-r--r--target/i386/cpu.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 512c69dddd..ac94013c4a 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1097,6 +1097,12 @@ typedef struct CPUCacheInfo {
} CPUCacheInfo;
+typedef struct CPUCaches {
+ CPUCacheInfo l1d_cache;
+ CPUCacheInfo l1i_cache;
+ CPUCacheInfo l2_cache;
+ CPUCacheInfo l3_cache;
+} CPUCaches;
typedef struct CPUX86State {
/* standard registers */
@@ -1286,6 +1292,7 @@ typedef struct CPUX86State {
/* Features that were explicitly enabled/disabled */
FeatureWordArray user_features;
uint32_t cpuid_model[12];
+ CPUCaches *cache_info;
/* MTRRs */
uint64_t mtrr_fixed[11];