diff options
| author | Robert Hoo <robert.hu@linux.intel.com> | 2018-07-05 17:09:55 +0800 |
|---|---|---|
| committer | Eduardo Habkost <ehabkost@redhat.com> | 2018-08-16 13:43:01 -0300 |
| commit | 3fc7c73139d2d38ae80c3b0bc963b1ac1555924c (patch) | |
| tree | e1b72cbe446ff851d1c370ec2cd70022af923bad /target/i386/cpu.h | |
| parent | 8c80c99fcceabd0708a5a83f08577e778c9419f5 (diff) | |
i386: Add CPUID bit and feature words for IA32_ARCH_CAPABILITIES MSR
Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as
SPEC_CTRL.
At present, mark CPUID_7_0_EDX_ARCH_CAPABILITIES unmigratable, per Paolo's
comment.
Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
Message-Id: <1530781798-183214-3-git-send-email-robert.hu@linux.intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Diffstat (limited to 'target/i386/cpu.h')
| -rw-r--r-- | target/i386/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/i386/cpu.h b/target/i386/cpu.h index b5c6686fe2..878444755f 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -690,6 +690,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */ +#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities*/ #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */ #define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */ |