diff options
| author | Chao Peng <chao.p.peng@linux.intel.com> | 2018-03-05 00:48:35 +0800 |
|---|---|---|
| committer | Eduardo Habkost <ehabkost@redhat.com> | 2018-03-12 15:59:46 -0300 |
| commit | e37a5c7fa459558b5020588994707fe3fdd6616e (patch) | |
| tree | f74043bcb92bd0c9cdbd07f9e82d9da2f006b60b /target/i386/cpu.h | |
| parent | be7773268d98176489483a315d3e2323cb0615b9 (diff) | |
i386: Add Intel Processor Trace feature support
Expose Intel Processor Trace feature to guest.
To make Intel PT live migration safe and get same CPUID information
with same CPU model on diffrent host. CPUID[14] is constant in this
patch. Intel PT use EPT is first supported in IceLake, the CPUID[14]
get on this machine as default value. Intel PT would be disabled
if any machine don't support this minial feature list.
Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
Signed-off-by: Luwei Kang <luwei.kang@intel.com>
Message-Id: <1520182116-16485-1-git-send-email-luwei.kang@intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Diffstat (limited to 'target/i386/cpu.h')
| -rw-r--r-- | target/i386/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 8d977ec567..ec2a771299 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -641,6 +641,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EBX_PCOMMIT (1U << 22) /* Persistent Commit */ #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */ #define CPUID_7_0_EBX_CLWB (1U << 24) /* Cache Line Write Back */ +#define CPUID_7_0_EBX_INTEL_PT (1U << 25) /* Intel Processor Trace */ #define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */ #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */ #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */ |