diff options
| author | Daniel P. Berrangé <berrange@redhat.com> | 2018-05-21 22:54:22 +0100 |
|---|---|---|
| committer | Eduardo Habkost <ehabkost@redhat.com> | 2018-05-21 18:59:01 -0300 |
| commit | d19d1f965904a533998739698020ff4ee8a103da (patch) | |
| tree | fa2bc1ae62248b71fd6a270475a84982cc5f0a10 /target/i386/cpu.h | |
| parent | 9802316ed6c19fd45b4c498523df02ca370d0586 (diff) | |
i386: define the 'ssbd' CPUID feature bit (CVE-2018-3639)
New microcode introduces the "Speculative Store Bypass Disable"
CPUID feature bit. This needs to be exposed to guest OS to allow
them to protect against CVE-2018-3639.
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Message-Id: <20180521215424.13520-2-berrange@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Diffstat (limited to 'target/i386/cpu.h')
| -rw-r--r-- | target/i386/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 8bc54d70bf..f0b68905de 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -685,6 +685,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */ +#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */ #define KVM_HINTS_DEDICATED (1U << 0) |