aboutsummaryrefslogtreecommitdiff
path: root/target/i386/cpu.c
diff options
context:
space:
mode:
authorYang Zhong <yang.zhong@intel.com>2017-11-22 15:27:56 +0800
committerPaolo Bonzini <pbonzini@redhat.com>2017-12-21 09:22:44 +0100
commitaff9e6e46a343e1404498be4edd03db1112f0950 (patch)
tree51e1e628cd6e5cee4edd6efabfd59fde0afbe68e /target/i386/cpu.c
parentc2380365d1d6c8c9f920651a2a429c75d977a589 (diff)
x86/cpu: Enable new SSE/AVX/AVX512 cpu features
Intel IceLake cpu has added new cpu features,AVX512_VBMI2/GFNI/ VAES/VPCLMULQDQ/AVX512_VNNI/AVX512_BITALG. Those new cpu features need expose to guest VM. The bit definition: CPUID.(EAX=7,ECX=0):ECX[bit 06] AVX512_VBMI2 CPUID.(EAX=7,ECX=0):ECX[bit 08] GFNI CPUID.(EAX=7,ECX=0):ECX[bit 09] VAES CPUID.(EAX=7,ECX=0):ECX[bit 10] VPCLMULQDQ CPUID.(EAX=7,ECX=0):ECX[bit 11] AVX512_VNNI CPUID.(EAX=7,ECX=0):ECX[bit 12] AVX512_BITALG The release document ref below link: https://software.intel.com/sites/default/files/managed/c5/15/\ architecture-instruction-set-extensions-programming-reference.pdf Signed-off-by: Yang Zhong <yang.zhong@intel.com> Message-Id: <1511335676-20797-1-git-send-email-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target/i386/cpu.c')
-rw-r--r--target/i386/cpu.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 82603e3130..325b52e325 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -437,9 +437,9 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
[FEAT_7_0_ECX] = {
.feat_names = {
NULL, "avx512vbmi", "umip", "pku",
- "ospke", NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, "avx512-vpopcntdq", NULL,
+ "ospke", NULL, "avx512vbmi2", NULL,
+ "gfni", "vaes", "vpclmulqdq", "avx512vnni",
+ "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
"la57", NULL, NULL, NULL,
NULL, NULL, "rdpid", NULL,
NULL, NULL, NULL, NULL,