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authorPeter Maydell <peter.maydell@linaro.org>2021-07-22 14:00:48 +0100
committerPeter Maydell <peter.maydell@linaro.org>2021-07-22 14:00:48 +0100
commitbeb191385882a2a283ce777d76b1a77e71813d14 (patch)
tree90418450177bdb5fe26016a189be61922374fbf3 /target/i386/cpu-param.h
parent423a4849db5244f9af152e3b69c5e0715f2ee7a5 (diff)
parentc2ffd7549b14373e9ca68eccd84fab141ffde646 (diff)
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210721' into staging
Atomic build fixes for clang-12 Breakpoint reorg # gpg: Signature made Wed 21 Jul 2021 20:57:50 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-tcg-20210721: (27 commits) accel/tcg: Record singlestep_enabled in tb->cflags accel/tcg: Hoist tb_cflags to a local in translator_loop accel/tcg: Remove TranslatorOps.breakpoint_check accel/tcg: Move breakpoint recognition outside translation accel/tcg: Merge tb_find into its only caller target/avr: Implement gdb_adjust_breakpoint hw/core: Introduce CPUClass.gdb_adjust_breakpoint target/i386: Implement debug_check_breakpoint target/arm: Implement debug_check_breakpoint hw/core: Introduce TCGCPUOps.debug_check_breakpoint accel/tcg: Use CF_NO_GOTO_{TB, PTR} in cpu_exec_step_atomic accel/tcg: Handle -singlestep in curr_cflags accel/tcg: Drop CF_NO_GOTO_PTR from -d nochain accel/tcg: Add CF_NO_GOTO_TB and CF_NO_GOTO_PTR target/alpha: Drop goto_tb path in gen_call_pal accel/tcg: Move curr_cflags into cpu-exec.c accel/tcg: Reduce CF_COUNT_MASK to match TCG_MAX_INSNS accel/tcg: Push trace info building into atomic_common.c.inc trace: Fold mem-internal.h into mem.h accel/tcg: Expand ATOMIC_MMU_LOOKUP_* ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/i386/cpu-param.h')
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