diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2023-09-16 21:41:32 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-11-06 18:49:34 -0800 |
| commit | 84e224d4226001ed73b8da42e4ad155cf80b1eef (patch) | |
| tree | 14fe28b2916545105109baacaaaa71261c97db9f /target/hppa | |
| parent | 63c427c615ea927fd93901f2dfeebb62ad3bf2bc (diff) | |
target/hppa: Decode d for bb instructions
Manipulate the shift count so that the bit to be tested
is always placed at the MSB.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/hppa')
| -rw-r--r-- | target/hppa/insns.decode | 4 | ||||
| -rw-r--r-- | target/hppa/translate.c | 6 |
2 files changed, 4 insertions, 6 deletions
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index ad454adcbb..b185523021 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -290,8 +290,8 @@ fmpysub_d 100110 ..... ..... ..... ..... 1 ..... @mpyadd # Conditional Branches #### -bb_sar 110000 00000 r:5 c:1 10 ........... n:1 . disp=%assemble_12 -bb_imm 110001 p:5 r:5 c:1 10 ........... n:1 . disp=%assemble_12 +bb_sar 110000 00000 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12 +bb_imm 110001 p:5 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12 movb 110010 ..... ..... ... ........... . . @rrb_cf f=0 movbi 110011 ..... ..... ... ........... . . @rib_cf f=0 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index f2b2933c88..e326f63866 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3172,13 +3172,12 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a) { TCGv_reg tmp, tcg_r; DisasCond cond; - bool d = false; nullify_over(ctx); tmp = tcg_temp_new(); tcg_r = load_gpr(ctx, a->r); - if (cond_need_ext(ctx, d)) { + if (cond_need_ext(ctx, a->d)) { /* Force shift into [32,63] */ tcg_gen_ori_reg(tmp, cpu_sar, 32); tcg_gen_shl_reg(tmp, tcg_r, tmp); @@ -3194,14 +3193,13 @@ static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a) { TCGv_reg tmp, tcg_r; DisasCond cond; - bool d = false; int p; nullify_over(ctx); tmp = tcg_temp_new(); tcg_r = load_gpr(ctx, a->r); - p = a->p | (cond_need_ext(ctx, d) ? 32 : 0); + p = a->p | (cond_need_ext(ctx, a->d) ? 32 : 0); tcg_gen_shli_reg(tmp, tcg_r, p); cond = cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); |