diff options
| author | Sven Schnelle <svens@stackframe.org> | 2024-03-21 19:42:27 +0100 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2024-03-27 12:15:25 -1000 |
| commit | bd1ad92ccfa48c44f001ebea17633ef61ff62642 (patch) | |
| tree | c32f0d03291dd7164cb0dc09d1e8f0724fe47bd7 /target/hppa | |
| parent | 578b8132b2666f7168b16422ac566684918a371e (diff) | |
target/hppa: Fix ADD/SUB trap on overflow for narrow mode
Fixes: c53e401ed9ff ("target/hppa: Remove TARGET_REGISTER_BITS")
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240321184228.611897-2-svens@stackframe.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/hppa')
| -rw-r--r-- | target/hppa/translate.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 2cb91956da..ceb739c54a 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1126,6 +1126,9 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 in1, if (is_tsv || cond_need_sv(c)) { sv = do_add_sv(ctx, dest, in1, in2); if (is_tsv) { + if (!d) { + tcg_gen_ext32s_i64(sv, sv); + } /* ??? Need to include overflow from shift. */ gen_helper_tsv(tcg_env, sv); } @@ -1217,6 +1220,9 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_i64 in1, if (is_tsv || cond_need_sv(c)) { sv = do_sub_sv(ctx, dest, in1, in2); if (is_tsv) { + if (!d) { + tcg_gen_ext32s_i64(sv, sv); + } gen_helper_tsv(tcg_env, sv); } } |