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authorRichard Henderson <richard.henderson@linaro.org>2021-12-13 09:38:38 -0800
committerRichard Henderson <richard.henderson@linaro.org>2021-12-23 17:47:01 -0800
commit05bfd4db08608bc4c22de729780c1f74612fbc0e (patch)
tree0828ad00145351584c77a6e3ec71952f79494372 /target/hppa
parentf18155a207dbc6a23f06a4af667280743819c31e (diff)
target/hppa: Fix deposit assert from trans_shrpw_imm
Because sa may be 0, tcg_gen_deposit_reg(dest, t0, cpu_gr[a->r1], 32 - sa, sa); may attempt a zero-width deposit at bit 32, which will assert for TARGET_REGISTER_BITS == 32. Use the newer extract2 when possible, which itself includes the rotri special case; otherwise mirror the code from trans_shrpw_sar, using concat and shri. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/635 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/hppa')
-rw-r--r--target/hppa/translate.c19
1 files changed, 12 insertions, 7 deletions
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 3b9744deb4..952027a28e 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -140,6 +140,7 @@
#define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i64
#define tcg_gen_extract_reg tcg_gen_extract_i64
#define tcg_gen_sextract_reg tcg_gen_sextract_i64
+#define tcg_gen_extract2_reg tcg_gen_extract2_i64
#define tcg_const_reg tcg_const_i64
#define tcg_const_local_reg tcg_const_local_i64
#define tcg_constant_reg tcg_constant_i64
@@ -234,6 +235,7 @@
#define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i32
#define tcg_gen_extract_reg tcg_gen_extract_i32
#define tcg_gen_sextract_reg tcg_gen_sextract_i32
+#define tcg_gen_extract2_reg tcg_gen_extract2_i32
#define tcg_const_reg tcg_const_i32
#define tcg_const_local_reg tcg_const_local_i32
#define tcg_constant_reg tcg_constant_i32
@@ -3204,19 +3206,22 @@ static bool trans_shrpw_imm(DisasContext *ctx, arg_shrpw_imm *a)
dest = dest_gpr(ctx, a->t);
t2 = load_gpr(ctx, a->r2);
- if (a->r1 == a->r2) {
+ if (a->r1 == 0) {
+ tcg_gen_extract_reg(dest, t2, sa, 32 - sa);
+ } else if (TARGET_REGISTER_BITS == 32) {
+ tcg_gen_extract2_reg(dest, t2, cpu_gr[a->r1], sa);
+ } else if (a->r1 == a->r2) {
TCGv_i32 t32 = tcg_temp_new_i32();
tcg_gen_trunc_reg_i32(t32, t2);
tcg_gen_rotri_i32(t32, t32, sa);
tcg_gen_extu_i32_reg(dest, t32);
tcg_temp_free_i32(t32);
- } else if (a->r1 == 0) {
- tcg_gen_extract_reg(dest, t2, sa, 32 - sa);
} else {
- TCGv_reg t0 = tcg_temp_new();
- tcg_gen_extract_reg(t0, t2, sa, 32 - sa);
- tcg_gen_deposit_reg(dest, t0, cpu_gr[a->r1], 32 - sa, sa);
- tcg_temp_free(t0);
+ TCGv_i64 t64 = tcg_temp_new_i64();
+ tcg_gen_concat_reg_i64(t64, t2, cpu_gr[a->r1]);
+ tcg_gen_shri_i64(t64, t64, sa);
+ tcg_gen_trunc_i64_reg(dest, t64);
+ tcg_temp_free_i64(t64);
}
save_gpr(ctx, a->t, dest);